Code discriminator for multiplexed binary offset carrier modulated signals
The present invention relates to the reception of Multiplexed Binary Offset Carrier MBOC modulated signals and similar such signals. One particular application of the invention is the reception of MBOC modulated navigation signals in a Global Navigation Satellite System GNSS.
The United States led Global Positioning System GPS is presently the GNSS in most common use. Navigation signals transmitted by GPS satellites are modulated using a Phase Shift Keying PSK modulation of a code onto a carrier signal having a designated carrier frequency.
The reference signal consists of an in-phase and quadrature-phase I and Q carrier modulated with the same code as the input signal. The comparison typically consists in multiplying the received signal by the I and Q reference to yield a demodulated signal.
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The demodulated signal is then integrated over a given time, usually the same as the period T G of the code, to output a value known as a correlation. As shown in FIG.
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Most conventional GPS receivers therefore compute just three sampled correlations simultaneously, using three reference signals offset in time from one another. The three correlations are usually referred to as gate values of Early E , Prompt P and Late L gates. The E and L gates are offset from one another by a time separation T DC , so that they can be considered to have trial delays.
So, as illustrated in FIG. An iterative algorithm can be used to arrive at this state. A best estimate of the true delay is then deemed to be the value of the trial delay of the P gate when the E gate value is equal to the L gate value as shown in FIG.
It is presently intended to improve the American GPS by adding new navigation signals to the system. The independent European Galileo system will use similar new navigation signals in both the same and new frequency bands.
While some of the new navigation signals will continue to use PSK modulation, most of them will be modulated using the new Binary Offset Carrier BOC modulation which is described first.
An important sub-set of BOC is called Multiplexed binary offset carrier and is described next. BOC modulation is like PSK in that it involves modulating a code onto a carrier. As seen in FIG. The sub-carrier rate f s is an integer multiple, or an integer-and-a-half multiple of the code rate f C. The standard notation for BOC modulation reads BOC f s , f C. When a received BOC signal is correlated using a matching locally generated BOC reference signal the resulting correlation function.
A number of techniques have been proposed for overcoming this problem with pure BOC. Fine et al, Proceedings of ION National Technical Meeting, January This technique takes advantage of the knowledge that adjacent peaks of the BOC correlation function.
Bump jumping allows a receiver to fully exploit the potential accuracy of BOC. However, there can be a significant waiting time before the delay estimate can be relied on. There is an elapsed time required to decide whether there is a false lock or not. Overall, the waiting time may range upwards to several seconds, which is certainly enough to have potentially disastrous consequences for a plane landing, ship docking or such like.
Worse, the receiver does not know that it has been in a false lock state until it actually jumps out of it. The bump jumping system therefore is not fail safe. A further difficulty has now been realised since the launch of the first test satellite GIOVE-A transmitting BOC signals in December Non-linear and linear distortion in the transmitting chain can easily cause appreciable asymmetry in the actual correlation function. It shows that the later negative secondary peak has the same amplitude as the positive primary peak.
In such a case the VEVL receiver must fail. For less extreme phase distortion—the unbalancing must degrade signal to noise performance, simply because it brings the amplitude of one of the secondary peaks closer to the amplitude of the primary peak.
This solution certainly eliminates false locks. However, this technique relies on a very complex receiver design. More fundamentally, it fails to realise the potential accuracy conferred by BOC modulation, because the shallower PSK correlation peak is relied on to resolve the delay estimate. But this method is again complex to implement and more fundamentally fails to realise the potential accuracy conferred by BOC modulation.
The solution—described in detail in patent application GB Multiplexed binary offset carrier MBOC has been proposed in an important modification of BOC. The proposal is authored and agreed by international experts G. Hein, J-Avial Rodriguez, S Wallner, J. Owen, J-L Issler and T.
When adopted it will add a further layer of complexity to reception of GNSS signals compared to ordinary BOC modulation, which is in turn more complicated than PSK modulation. It offers improved accuracy and better rejection of multi-path. The basis is to make the sub-carrier modulation a linear superposition of BOC 1,1 and BOC 6,1. The currently favoured alternative is in the frequency domain multiplexing where there is continuous modulation with unequal amplitudes of the two components CBOC.
Whichever form is adopted makes no difference to the invention. Current proposals divide power into data channel and pilot channel. One current proposal assumes a division of power and with no BOC 6,1 component in the data channel, putting it all in the pilot channel.
Whatever proportions are finally decided makes no difference to the invention. The difference from BOC is clearly seen in the form of a doubly periodic modulation with half periods described by two different sub-chip widths T S1 and T S2. When recovered in the conventional single estimate receiver an even more complicated correlation function as in FIG. We shall adopt the notation. The present invention overcomes the problem of tracking MBOC.
The solution is to eliminate the problem by eliminating the correlation function. According to a first aspect of the present invention, there is provided a receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite modulation function which is the sum of two different sub-carriers with unequal rates and which rates are different to the code rate the receiver comprising processing means arranged to:.
The present invention further provides a receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising processing means arranged to:. The essence of some embodiments of the invention is that it estimates the signal delay in three independent ways and then combines all three estimates to arrive at one overall signal delay estimate.
If prior art is applied to MBOC the receiver would correlate the modulation in the received signal with only a single modulation function, which is the combination of the code modulation and the composite sub-carrier modulation.
Up to now dealing with the correlation function. In some embodiments of the invention the delay in the MBOC signal is estimated in three different and independent ways—in a triple estimate.
A first non-ambiguous lower accuracy estimate is used to resolve the ambiguities in a second higher accuracy estimate. A second estimate is derived only from the phase of low frequency component sub carrier modulation in the MBOC signal and ignores the code and the high frequency component sub carrier. A third estimate is derived only from the phase of high frequency component sub carrier modulation in the MBOC signal and ignores both the code and the lower frequency sub-carrier.
The code estimate resolves the ambiguity in the second estimate which in turn resolves the ambiguity in the third even higher accuracy estimate. A four-loop receiver can be used for the optimal triple estimate of the delay in a selected MBOC transmission.
In some embodiments an inner delay-locked loop DLL tracks the delay as embodied in the code phase; a lower frequency sub-carrier locked loop SLL 1 independently tracks the same delay as embodied in the first component sub-carrier phase, while a higher frequency sub-carrier locked loop SLL 2 independently tracks the same delay as embodied in the second component sub-carrier phase.
Thus three independent delay estimates are calculated.
All four loops may operate simultaneously, independently yet co-operatively. By virtue of the triple estimate principle in some embodiments of this invention the MBOC correlation function. The SLL 1 however locks to the nearest peak of the continuous first sub-carrier correlation function—which is a triangular function of periodicity of the low frequency sub-carrier component.
This loop estimate has higher accuracy but has an inherent ambiguity in integer multiples of first sub-carrier half cycles.
For, in a further step, the ambiguity in this SLL 1 estimate is automatically and instantly resolved by comparison with the DLL estimate. The SLL 2 however, in some embodiments, locks to the nearest peak of the continuous second sub-carrier correlation function—which is a triangular function of periodicity of the high frequency sub-carrier component. This loop estimate has higher accuracy but has an inherent ambiguity in integer multiples of second sub-carrier half cycles.
For, in a further step, the ambiguity in this SLL 2 estimate is automatically and instantly resolved by comparison with the corrected SLL 1 estimate. The combination of SLL 2 , SLL 1 and DLL estimates can now provide the inherently higher accuracy due to MBOC modulation on the signal comparing with PSK on the basis of the same chip rate , with the ambiguity now resolved. Because the allocated power to the lower frequency sub-carrier is much higher than allocated to the higher frequency sub-carrier an optimal linear combination may be made of the two SLL estimates to generate a fourth estimate with even higher accuracy.
Simulations show smooth consistent operation of this joint estimation process even in conditions of poor signal to noise. The four-loop receiver can be implemented with the same variety of options that are available to two loop receivers. Various possible phase and frequency discriminators can be used. Various possible discriminators for the two SLLs can also be used.
A variety of standard discriminators for the DLL loop can also be used. In particular the options between coherent early late processing CELP and non-coherent early late processing NELP continue to be available not only to the code discriminator on the DLL, but also for the sub-carrier tracking on the SLLs.
Known technologies and variants, including methods for reducing effect of multipath and currently used in two-loop system will transfer to the new four loop system without complication. In some embodiments the received signal could more than two, for example three sub-carrier modulation components, in which case a quadruple estimate could be made.
Preferred embodiments of the invention are now described, by way of example only, with reference to the accompanying drawings. The antenna 2 feeds the received signal to a pre-amplifier 3 , which includes a filter for filtering the received signal, a circuit for blocking strong interfering signals and a Low Noise Amplifier LNA for amplifying the received signal. The LNA effectively sets the receiver's noise figure, normally around 2 dB, and provides around 30 dB gain.
The pre-amplifier 3 feeds the filtered, amplified signal to a down-converter 4 for a first stage down-conversion of the signal to a suitable intermediate frequency IF. The signal is down-converted in multiple stages and filtered to eliminate unwanted image signals.
The down-converter 4 feeds the down-converted signal to an Analogue to Digital Converter ADC 5 for converting the signal to the digital domain. The ADC 5 can quantise the signal to one, two or more bits.
In this embodiment, because the ADC 5 uses multi-bit quantisation, the receiver 1 incorporates an automatic gain control AGC circuit 6 to maintain proper distribution of the signal across the quantisation levels. The output of the AGC circuit 6 feeds back to the down-converter 4 to enable control of the signal level input to the ADC 5 and hence maintain proper amplitude distribution of the signal output by the ADC 5.
The ADC 5 is arranged to output the digital signal u t to the triple-estimator 8. This has a correlator stage 9 and a processing stage In this embodiment, the triple estimator 8 is implemented in hardware. A clock signal c t from reference oscillator at 7 is provided to the down-converter 4 , ADC 6 and the triple estimator 8.
The input signal u t splits into an upper in-phase and lower quadrature arm and is processed through four stages.
The incoming signal is mixed with replica carrier, sub carrier 2 , and sub carrier 1 and code waveforms, each generated by separate digitally controlled oscillators DCO 12 , 17 2 , 17 1 18 respectively.
The resulting signal combinations are accumulated over the code period and eight correlation results formed. The extreme right of the diagram shows the interaction through a data bus to the microprocessor Here s 1 is the BOC 1,1 component while s 2 is the BOC 6,1 component. It is necessary to note a restriction on the integers. Comparing 1 with 2 it is evident that if n 1 is an odd number then n 2 must be an odd number; or if n 1 is an even number then n 2 must be an even number, otherwise the correct shape of the composite modulation is not preserved.
Irrespective of these offset delays it should be understood that the actual sub-carrier delay and the code delay for any actually received signal are still the same as in 1. The multiplier 13 then multiplies the digital signal u t with reference r I t and the I signal filter 14 filters the result to output an in-phase signal v I t in the I channel; while the Q signal multiplier 15 multiplies the digital signal u t with reference r Q t and the Q signal filter 16 filters the result to output quadrature signal v Q t in the Q channel.
Eight demodulated signals are generated: I channel sum sub carrier P gate code P gate signal v III t ; I channel sub carrier 1 E 1 gate code P gate signal v IE1I t ; I channel sub carrier 1 L 1 gate code P gate signal v IL1I t , I channel sub carrier 2 E 2 gate code P gate signal v IE2I t , I channel sub carrier 2 L 2 gate code P gate signal v IL2I t ; I channel sum sub carrier P gate code E gate signal v IIE t ; I channel sum sub carrier P gate code L gate signal v IIL t ; Q channel sum sub carrier P gate code P gate signal v QII t.
The demodulated signals v III t , v IE1I t , v IL1I t , v IE2I t , v IL2I t , v IIE t , v IIL t and v QII t , are then integrated by integrators 29 to 34 respectively. The integrators 29 to 34 perform the integration over a fixed time, which in this embodiment is the same as the code period T G. In other embodiments, the integration time can be an integer multiple of the code period T G , so that the integration time is typically of the order of a few milliseconds in total.
The output of each of the integrators 29 to 34 is sampled by the processing stage 10 at the end of each fixed time and the integrators 29 to 34 reset to zero. The purpose of introducing this index k is to clarify the nature of a time series being generated—the actual practical software does not need to implement a count notation. This function is not easily displayed. This is shown in FIG. It can be appreciated that, when the I channel sub carrier 1 E 1 gate code P gate correlation w IE1I [k] has the same value as the I channel sub-carrier 1 L 1 gate of code P gate the correlation w IL1I [k], i.
Similarly, when the I channel sub carrier 2 E 2 gate code P gate correlation w IE2I [k] has the same value as the I channel sub carrier 2 L 2 gate code P gate correlation w IL2I [k] i. Similarly, when the I channel sum sub carrier P gate code E gate correlation w IIE [k] has the same value the I channel sum sub carrier P gate code L gate correlation w IIL [k], i. Similarly when phase lock has been achieved the Q channel correlation w QII [k] is zero, i.
Consequently, the processing stage 10 carries out a subtraction step 35 1 that subtracts correlation w IE1I [k] from the correlation w IL1I [k] to give a sub-carrier 1 difference correlation w IQ1I [k]. According to one embodiment the principle of coherent early-late processing CELP may be adopted. Consequently, the processing stage 10 carries out a subtraction step 35 2 that subtracts correlation w IE2I [k] from the correlation w IL2I [k] to give a sub-carrier 2 difference correlation w IQ2I [k].
Consequently, the processing stage 10 carries out a subtraction step 36 that subtracts correlation w IIE [k] from the correlation w IIL [k] to give a code difference correlation w IIQ [k]. It should be noted that in this account an E gate is subtracted from an L gate in order to ensure correct polarity of loop correction in terms of a code and sub-carrier delay estimate. In an equivalent description an L gate is subtracted from an E gate, in order to ensure correct polarity of loop correction as expressed in terms of a code and sub-carrier phase estimate.
A simplest procedure to derive a corrected estimate combines the two. All processing actions will be described and also summarised in pseudo code.
Execution of this block of computer code is synchronised to every correlation and is updated here according to a count k. Correlations w III [k], w IQ1I [k], w IQ2I [k], w IIQ [k] and w QII [k] are input to this processing block. Also responsive DLL gate widths T DC [k] and SLL 1 gate width T D1 [k] are output—which vary in response to conditions.
The processing stage 1 is a limiter to estimate the sign of the I sub-carrier P gate and code P gate correlation w III [k] which may be either positive or negative. But because of the lower power in the MBOC component the difference in accuracy between the SLL 1 and SLL 2 estimates is not so large. Consequently it is worth while to form an optimal linear mix of the two estimates, after the values have been corrected, as is shown in line 8 to get an estimate which is the best of all.
With increasing count and in the realistic presence of noise these errors go to zero on average i. The remainder of the processing block is concerned with corrections when needed to the potentially ambiguous estimates. This estimate is therefore booted, i. Further, the DLL gate width is expanded from whatever is its current narrower width T DC to a full chip width T C as in 12 1.
The purpose of this manoeuvre is to speed up acquisition because it is likely that the DLL is in the process of acquiring lock.
Otherwise it may be that the filtered difference between the two estimates has not exceeded half a sub-chip width. A gain term K F controls the response time of this difference filter. Further, the code gate width T DC decrements exponentially, and in due course, over sufficient number of iterations this width will settle asymptotically on a minimum value—made here to be equal to the sub-chip width T S1 as in 14 1.
The settling time of this is determined by a controller gain K D. The point of controlling the DLL gate downwards to this minimum is in order to minimise the noise in the DLL loop, which if excessive could trigger a false decision in line 9 1.
Alignment of the adjusted estimates preserves the correct shape of the multiplexed subcarriers as in FIG. In the event of a detected slip the SLL 1 gate width is augmented, anticipating an acquisition state.
If no slip is detected this gate width is allowed to relax back to the steady state value. This is therefore booted, i. Further, the SLL 1 gate width is expanded from whatever is its current narrower width T D1 to a full sub-chip width T S1 in 12 2.
The purpose of this manoeuvre is to speed up acquisition because it is likely that the SLL 1 is in the process of acquiring lock. Otherwise it may be that the filtered difference between the two estimates has not exceeded a full sub-chip width. Further, the gate width T D1 decrements exponentially, and in due course, over sufficient number of iterations this width will settle asymptotically on a minimum value—made here to be equal to the sub-chip width T S2.
The point of controlling the SLL 1 gate downwards to some minimum is in order to minimise the noise in the SLL 1 loop, which if excessive could trigger a false decision at 9 2. In this way the receiver may operate in the lowest possible carrier to noise density ratio. The system as described above with reference to FIGS. As an essential qualification is noted that the system fails if the loops lose lock. But this is true of all loop-based systems.
Theory finds however that this restriction on the allowed range of CNDR and B L. The value of the DLL gate width T DC , which controls the DLL discriminator action is an automatic compromise.
To maximise speed of acquisition it is switched to the highest value which is the chip width T C This gives the fastest response of the DLL in the initial acquisition. In a detected steady state the relaxation of T DC down to sub-chip width T S1 will however minimise the noise in the DLL estimate and extend the basic performance envelope. Similarly the value of the SLL 1 gate width T D1 , which controls the SLL 1 discriminator action is an automatic compromise. To maximize speed of acquisition it is switched to the highest value which is the sub-chip width T S1.
This gives the fastest response of the SLL 1 in the initial acquisition. In a detected steady state the relaxation of T D1 down to the smaller sub-chip width T S2 will however minimise the noise in the SLL 1 estimate and extend the basic performance envelope. The failure condition are however fail safe since the receiver can always measure for itself when this condition has arisen.
It was claimed that the prior art receiver designed according to the VEVL, amongst other problems, is vulnerable to phase distortion see FIG. The same effect manifests itself here as non integer shifts to the two SLL estimates. The corresponding modifications needed in the pseudo code can be done in a number of ways.
Practical Implementation The correlator architecture of a GNSS BOC receiver requires relatively few changes compared to a GNSS PSK receiver in order to implement the triple estimate in a quadruple loop technique. This process is equivalent in both hardware and software receivers. The initialisation involves setting up the software and starting the correlator channels running. After initialisation the software enables the software interrupts. The tracking task reads the accumulator values, estimates the navigational data state and updates all four loops with new estimates of carrier 1 , sub carrier, sub carrier 2 and code phase.
The measurement task provides the detailed measurements required to form the navigation solution such as reading the carrier, the two sub carriers and code DCO values and necessary counters in the correlator. Under these essential tasks priority can be given to the various navigational tasks.
Table T 1 shows the hardware requirements of each correlator channel based on receiver architecture designed to operate at an intermediate frequency IF of The hardware requirements of the quadruple loop receiver as detailed in Table 1 are easily achievable 12 channels or more with most modern ASIC and FPGA designs.
Two levels of complexity are distinguished—the minimum components needed for the outer loop embodying a DLL—as given in the detailed description and FIG. A further level of complexity requires the additional components as shown in extreme right columns for the purposes described in the next section. TABLE 1 Hardware requirements of triple loop architecture per channel.
In the standard literature numerous improvements and alternatives are described to enable double loop implementation of standard PSK-CDMA. Without exception, after appropriate modification these may be applied to the quadruple loop receiver of MBOC. Not shown in FIG. From these may be integrated to corresponding correlations every T seconds to w IEnE [k], w ILnE [k], w IEnL [k], w ILnL [k], w QEnI [k], w QLnI [k], w QIE [k], w QIL [k] respectively.
These correlations may be used to enhance and generalise operation of the invention in many different ways.
The invention admits the standard technique of carrier aiding—the technique of importing into the delay estimate a correction proportional to the Doppler frequency. The computation to error sequences according to , , and utilised only one of many possible discriminators. The standard alternatives available in the dual-loop single-estimate conventional PSK receivers may be adopted here, after appropriate modification, and in particular non-coherent early late processors NELP.
Van Dierendonck et al ION National Technical Meeting San Diego Calif. This concept requires a frequency locked loop FLL instead of a PLL in the outer loop. This type of system is readily incorporated into the triple estimate concept for MBOC-GNSS requiring however some of the additional correlations identified from 39 to The chosen parameters are exactly the same in the two FIGS.
The aim here is not only to demonstrate the anti-slip fail safe nature of the quadruple loop but also to show a typical acquisition process. Simulation values are deliberately chosen for the most stringent test of possible operation. This carrier to noise density ratio is significantly lower than usual test conditions for GNSS signals. The test here shows that the algorithm will simultaneously acquire all three estimates and instantaneously correct the SLL 1 estimate from the DLL estimate and the SLL 2 estimate from the SLL 1 estimate, even during the dynamic process when the loops are locking up.
Tracking performance depends on the difference between the actual code delay and the initial setting of the loop estimates after an initial search. The rising dotted curve in the upper graph is the DLL estimate. Acquisition by the DLL responds immediately but the other loops hardly move until count 21 msec ; then SLL 1 is booted into action and immediately after SLL 2. The long dashed curve for SLL 1 shows that it requires only two steps to get to the final estimate; while the continuous curve for SLL 2 shows the expected smaller increments.
The whole point and purpose of the invention is demonstrated here: Acquisition is complete on a step at around 50 counts or 1 s. The simulation also monitors the tracking of the third carrier tracking loop which here is a 2 nd order PLL.
The continuous track on the lower graph of FIG. The dotted and dashed curves on the lower graph show the dynamic response of the gate widths T DC and T D1 —opening out when there is a perceived need for rapid acquisition and then settling down to lower levels T S1 and T S2 respectively in due time.
Similar results with additive electrical noise actually present are shown in example from FIG. The acquisition time is accordingly a random variable.
It can take longer; or it can be shorter. The quasi-random nature of the acquisition process is evident. Yet there is a definite acquisition. The widely fluctuating dotted curve is the DLL estimate. The broken curve is the SLL 1 estimate. The continuous curve is the joint optimal linear estimate computed as described. The much lower timing error in the optimal estimate is evident.
The advantage of some embodiments of the present invention over the prior art may include the following: The present invention avoids locking on a wrong peak false node , provided uncritical requirements on input carrier to noise density ratio and loop bandwidth are met, since there is no multi-peaked one-dimensional correlation function in the first place. Equivalently the more complicated routines of Esq. The receiver is therefore fail safe, in the sense that after loop convergence the highest quality estimate is immediately and continuously available thereafter.
The described embodiments of the invention are only examples of how the invention may be implemented. Modifications, variations and changes to the described embodiments will occur to those having appropriate skills and knowledge.
These modifications, variations and changes may be made without departure from the scope of the invention defined in the claims and its equivalents. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which arc different to the code rate, Try the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.
Receiver of multiplexed binary offset carrier MBOC modulated signals US B2. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which arc different to the code rate, the receiver comprising processing means arranged to: The invention claimed is: A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising a processor arranged to: A receiver according to claim 1 wherein the processor is arranged to make a correction to at least one of the second and third estimates of delay to correct for phase distortion.
A receiver according to claim 2 wherein the correction is a non-integer multiple of the sub-chip width. A receiver according to claim 1 wherein a control means is arranged to determine a combined estimate of delay from the third delay estimate and the further delay estimate.
A receiver according to claim 5 wherein the processor is arranged, in determining the further delay estimate, to add the first delay difference to the second estimate of delay and the second delay difference to the third estimate. A receiver according to claim 9 wherein the processor is arranged to use the correlations to generate error estimations for the delay estimates, and to update the delay estimates based on the error estimations.
A receiver according to claim 9 wherein the at least one reference code signal includes an early reference code signal and a late reference code signal separated by a gate width time difference. A receiver according to claim 12 wherein the processor is arranged to combine the correlations in a manner which varies as the delay approaches the actual delay to determine the error estimations. FIELD OF THE INVENTION The present invention relates to the reception of Multiplexed Binary Offset Carrier MBOC modulated signals and similar such signals.
CNA , CNB , EPA1 , EPB1 , US , WOA1. The University Of Surrey. BiBTeX , EndNote , RefMan. Patent Citations 18 , Non-Patent Citations 23 , Referenced by 6 , Classifications 7 , Legal Events 2. USPTO , USPTO Assignment , Espacenet. Global positioning system GPS receiver for recovery and tracking of signals modulated with P-code. System and method for demodulating global positioning system signals. Method for satellite tracking and extracting the signal by correlation.
Spread spectrum receiver using a pseudo-random noise code for ranging applications in a way that reduces errors when a multipath signal is present. Global positioning system code phase detector with multipath compensation and method for reducing multipath components associated with a received signal. Hardware architecture for processing galileo alternate binary offset carrier AltBOC signals. Satellite-based positioning receiver with correction of cross correlation errors. Global navigation satellite system GNSS receivers based on satellite signal channel impulse response.
Global positioning receiver with cross-correlation error correction. Receiver of multiplexed binary offset carrier mboc modulated signals. Method for the acquisition of a radio-navigation signal by satellite. A method and device for demodulating galileo alternate binary offset carrier altboc signals.
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